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PRELIMINARY
CXD1944R
IEEE1394 3-port 200Mbps Cable Transceiver/Arbiter
Description The CXD1944R is a PHY chip which suppor ts 100/200Mbps speeds and performs cable interface and bus arbitration. It conforms to the high performance serial bus IEEE1394-1995 standard. The structure is 0.4m CMOS and it operates on a single 3.3V power supply. 64 pin LQFP (plastic)
Features * Conforms to IEEE1394-1995 * Single 3.3V power supply * Supports 100/200Mbps speeds * Automatic power down for unused ports * Power down mode to conserve energy * Supports short reset operation * Supports ping for optimization of a Gap_count Absolute Maximum Ratings * Supply voltage * Input voltage * Output voltage * Storage temperature VDD VI -0.5 to +4.6 V Applications When used with a LINK chip (e.g. CXD1940R), allows configuration of a high-speed digital serial interface. Structure 0.4m CMOS monolithic IC 1000 mW VSS -0.5 to VDD +0.5 V -20 to +70 -55 to +150 C C Package 64-pin plastic LQFP (VQFP) Operating Conditions * Supply voltage VDD 3.0 to 4.5 -20 to +75 V C * Operating temperature Ta
VO VSS -0.5 to VDD +0.5 V Tstg PD
* Operating temperature Ta * Allowable power dissipation
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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PE96431-ST
CXD1944R
Block Diagram
CMC/LKON PC0 PC1 PC2 TIO TEST0 TEST1 LDSEL CPS LPS XISO SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 Arbitration and Control State Machine Logic Link Interface I/O Cable Port 2 TPB2+ TPB2- TPA3+ TPA3- Cable Port 3 TPB3+ TPB3- TB1 TB2 TB3 R1 R0 XI XO FLT
TPA1+ TPA1-
Cable Port 1 TPB1+ TPB1-
TPA2+ TPA2-
Received Data Decoder and Retimer
Voltage and Current Generator Crystal Oscillator PLL System and Transmit Clock Generator
XRESET
Transmit Data Encoder
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CXD1944R
Pin Configuration
55 PLLVDD 53 PLLVSS 52 PLLVSS 58 DVDD 51 AVDD 64 AVSS 63 AVSS 61 AVSS 50 AVSS 49 AVSS 48 TB3 47 TB2 46 TB1 45 TPA1+ 44 TPA1- 43 TPB1+ 42 TPB1- 41 AVSS 40 TPA2+ 39 TPA2- 38 TPB2+ 37 TPB2- 36 TPA3+ 35 TPA3- 34 TPB3+ 33 TPB3- CAP 17 TIO 18 XSLOW 19 DVDD 20 TEST1 21 TEST0 22 CPS 23 AVDD 24 AVDD 25 AVSS 26 CMC/LKON 27 PC0 28 PC1 29 PC2 30 CNA 31 AVSS 32 62 XISO
XRESET LPS LREQ VDD-IO LDSEL DVDD PWD DVSS SYSCLK
1 2 3 4 5 6 7 8 9
DVSS 10 CTL0 11 CTL1 12 D0 13 D1 14 D2 15 D3 16
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54 FLT
57 XO
60 R1
59 R0
56 XI
CXD1944R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Symbol XRESET LPS LREQ VDD-IO LDSEL DVDD PWD DVSS SYSCLK DVDD CTL0 CTL1 D0 D1 D2 D3 CAP TIO XSLOW DVDD TEST1 TEST0 CPS AVDD AVDD AVSS CMC/LKON I/O I I I Supply I Supply I Supply OUT Supply I/O I/O I/O I/O I/O I/O I I/O I Supply I I I(A) Supply Supply Supply I/O Description Reset input. Asserts at LOW. A power-on reset signal can be generated by adding a 0.1F capacitor. LINK power supply status. LINK power supply is connected. LINK request input. IO power supply. LINK delay select. Digital circuit power supply. Power down input. Digital circuit ground. System clock output; 49.152MHz clock to LINK. Digital circuit power supply. I/O of bidrectional control signals for LINK. I/O of bidrectional control signals for LINK. I/O of bidirectional data signals for LINK. I/O of bidirectional data signals for LINK. I/O of bidirectional data signals for LINK. I/O of bidirectional data signals for LINK. Connect to ground via 0.1F capacitor when a 5V LINK is used. Connect to VSS or VDD. If then connected to VDD, short reset mode is selected. When XSLOW = LOW, a device acts as a 100M PHY. Normally connected to VDD. Digital power supply. Test mode control. Normally connected to ground. Test mode control. Normally connected to ground. Cable power status input. Normally connected to cable power. Analog circuit power supply. Analog circuit power supply. Analog circuit power ground. Configuration Manager Capable input, LINK ON clock (6MHz) output. When LPS = LOW and a LinkOn packet is received, the 6MHz clock signal continues to be output. Connect to VDD or VSS with a 10K resister. The configuration management function is indicated when connected to VDD. Power Class input (LSB). Power Class input. Power Class input (MSB). Cable Not Active output. This output is debounced. Analog circuit power ground. Port3, Cable Pair B-. Port3, Cable Pair B+.
28 29 30 31 32 33 34
PC0 PC1 PC2 CNA AVSS TPB3- TPB3+
I I I O Supply I/O(A) I/O(A)
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CXD1944R
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol TPA3- TPA3+ TPB2- TPB2+ TPA2- TPA2+ AVSS TPB1- TPB1+ TPA1- TPA1+ TB1 TB2 TB3 AVSS AVSS AVDD PLLVSS PLLVSS FLT PLLVDD XI XO DVDD R0 R1 AVSS XISO AVSS AVSS
I/O I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) Supply I/O(A) I/O(A) I/O(A) I/O(A) O(A) O(A) O(A) Supply Supply Supply Supply Supply O(A) Supply I(A) O(A) Supply I(A) O(A) Supply I Supply Supply Port3, Cable Pair A-. Port3, Cable Pair A+. Port2, Cable Pair B-. Port2, Cable Pair B+. Port2, Cable Pair A-. Port2, Cable Pair A+. Analog circuit power ground. Port1, Cable Pair B-. Port1, Cable Pair B+. Port1, Cable Pair A-. Port1, Cable Pair A+.
Description
Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power down. Corresponds to one port. Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power down. Corresponds to one port. Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power down. Corresponds to one port. Analog circuit power ground. Analog circuit power ground. Analog circuit power supply. PLL circuit power ground. PLL circuit power ground. PLL loop filter. PLL circuit power supply. Crystal oscillator (24.576MHz100ppm). The optimum values for the 100k resistor and 20pF capacitor. Crystal oscillator (24.576MHz100ppm). The optimum values for the 100k resistor and 20pF capacitor. Digital circuit power supply. Reference resistance pin. Connect R1 and R0 with 6.8k5% resistor. R0 may be connected to ground. Reference resistance pin. Connect R1 and R0 with 6.8k5% resistor. R0 may be connected to ground. Analog circuit power ground. XISO = LOW indicates isolation barrier which enables digital differentiator. Analog circuit power ground. Analog circuit power ground.
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CXD1944R
Recommended Operating Conditions Item Supply voltage High level input Low level input Differential input Differential input Differential input Common input Common input Differential input jitter Differential input skew Differential input jitter Differential input skew Output current (1) Symbol VDD VIH VIL VID-100 VID-200 VID-ARB VCM-100 VCM-200 JTT100 SKW100 JTT200 SKW200 IOH/IOL IO XRESET, LPS, LREQ, CTL0 XRESET, LPS, LREQ, CTL0 Cable input, 100Mbps Cable input, 200Mbps Cable input, Arbitration TpB Cable input, 100Mbps or speed signaling off TpB Cable input, 200Mbps, speed signaling on Cable input, 100Mbps Between TpA and TpB, 100Mbps Cable input, 200Mbps Between TpA and TpB, 200Mbps SYSCLK, CTL0, CTL1, D0, D1, D2, D3, CMC/LKON TB1, TB2, TB3 12 -1.3 9.68 142 132 171 1.165 0.935 Conditions Min. 3.0 0.8VDD 0.2VDD 260 260 260 2.515 2.515 1.08 0.80 0.50 0.55 Typ. 3.3 Max. 3.6 Unit V V V mV mV mV V V ns ns ns ns mA mA
Electrical Characteristics Driver Item Differential output voltage Common mode current (2) Speed signal common mode current (2) Symbol VOD ICM ICM-SP Conditions 55 load Min. 172 Typ. Max. 265 0.22 -2.53 20 Unit mV mA mA mV
Driver on, speed signaling off -0.40 200Mbps speed signaling on Driver off, speed signaling off -4.84
Common mode voltage when driver is off (2) VOFF
NOTES: 1. For output current, all source current is positive (+) and sink current is negative (-). 2. Common mode current is the average value of the currents output from TPB+ and TPB-. The same applies to TPA+ and TPA-.
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CXD1944R
Receiver Item Common mode input current Differential input impedance Symbol IIC ZID Conditions Driver off Driver off Min. -20 15 24 Differential input threshold Arbitration differential input threshold VTH VTH+ VTHZ VTH- Speed signal detection threshold Cable bias detection threshold VTH-SP VTH-CB "1" input "Z" input "0" input TB-TPA common mode potential TPB common mode input 49 0.6 -30 168 -89 89 -168 131 1.0 30 Typ. Max. 20 Unit A k pF mV mV mV mV mV V
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CXD1944R
Device Item Supply current Symbol IDD VDD = 3.6V VDD = 3.6V when cable is not connected IDD-PD I/O supply voltage VDD-IO VDD = 3.6V, Power down mode When a 5V LINK is used When a 3V LINK is used High level output Low level output VOH VOL SYSCLK, CTL0, CTL1, D0, D1, D2, D3, CMC/LKON, IOH = 12mA, VDD = min. SYSCLK, CTL0, CTL1, D0, D1, D2, D3, CMC/LKON, IOL = 12mA, VDD = max. XRESET, LPS, LREQ, PWD, CTL0, CTL1, D0, D1, D2, D3 XRESET, LPS, LREQ, PWD, CTL0, CTL1, D0, D1, D2, D3 XRESET, LPS, LREQ, PWD, CTL0, CTL1, D0, D1, D2, D3, VI = 0V or VDD SYSCLK, CTL0, CTL1, D0, D1, D2, D3, CMC/LKON 2 200k resistor CPS pin at 1.85V 5.5 20 1.665 IR1 = 100A 0.635 7.5 30 2.015 0.761 0.6VDD 0.4VDD 10 40 4.5 3.0 VDD-0.4 0.4 Condition Min. Typ. Max. 100 50 10 5.5 3.6 Unit mA mA mA V V V V V V A A ms V A V V
High level input threshold VTH+ Low level input threshold Input leak current Output leak current when output is off Power up reset time CPS input threshold CPS input current TB output voltage R1 pin output voltage VTH- IIL IOZ TPWR VTH-CPS ICPS VO VR1
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CXD1944R
I/O Pin Capacitance Item Input pin capacitance Output pin capacitance Symbol CIN COUT Conditions XRESET, LPS, LREQ, PC0, PC1, PC2, CPS SYSCLK CTL0, CTL1, D0, D1, D2, D3, CMC/LKON Min. Typ. Max. 11 11 11 Unit pF pF pF
Input/Output capacitance CI/O
AC Characteristics Item Output jitter Output skew Output rise time Output fall time Setup time Symbol JTT SKW Tr Tf Tsu TPA, TPB Between TPA and TPB TPA, TPB, 10 to 90%, RL = 55, CL = 10pF TPA, TPB, 90 to 10%, RL = 55, CL = 10pF LREQ, CTL0, CTL1, D0, D1, D2, D3 relative to SYSCLK, LDSEL = HIGH LREQ, CTL0, CTL1, D0, D1, D2, D3 relative to SYSCLK, LDSEL = LOW Hold time Thd LREQ, CTL0, CTL1, D0, D1, D2, D3 relative to SYSCLK, LDSEL = HIGH LREQ, CTL0, CTL1, D0, D1, D2, D3 relative to SYSCLK, LDSEL = LOW Output delay time Output disable time(1) Td Thz CTL0, CTL1, D0, D1, D2, D3 from SYSCLK CTL0, CTL1, D0, D1, D2, D3 from SYSCLK 5 0 2 7 2.5 1.5 11 0.0 Conditions Min. Typ. Max. 0.25 0.15 2.2 2.2 Unit ns ns ns ns ns ns ns ns ns ns
NOTE: 1. When control of CTL0, CTL1 and D0 to 3 passes from PHY to LINK. Refer to the section on Transmit.
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CXD1944R
Switching Waveforms
SysCLK tsu LReq, Ctl, Data LReq, Ctl, Data setup time and hold time thd
SysCLK td
Ctl, Data
SysCLK tHZ Hi-Z
Ctl, Data
Ctl, Data Output Delay
Internal Register MSB Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 0 0 0 RHB IBR 0 BSTAT1 BSTAT2 BSTAT3 CPStat IDidIt Ch1 Ch2 Ch3
Illegal LReq
LSB 1 2 Physical-ID GC NP = 00011 Con1 Con2 Con3 0 Chip Rev Reserved 0 0 Slow Pin Slow Bit ArbRstReq 0 0 0 0 P1Fast P2Fast P3Fast 0 3 4 5 6 R 7 CPS
0
SPD = 01 ASTAT1 ASTAT2 ASTAT3 LoopInt CPStatInt
Reserved
Ping Timer [15 : 8] Ping Timer [7 : 0]
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CXD1944R
Name Physical-ID R CPS RHB IBR GC SPD NP ASTAT(n) BSTAT(n) Ch(n) Con(n) P(n) Fast LoopInt CPStatInt CPStat IDidIt IllegalReq ChipRev Slow Pin Slow Bit ArbRstReq Ping Timer
Size 6 1 1 1 1 6 2 4 2 2 1 1 1 1 1 1 1 1 4 1 1 1 16
Type R R R R/W R/W R/W R R R R R R R R/W R/W R R R R R R/W R/W R
Description The address number of this node. Determined during Self-ID. Indicates that this node is the root. Cable power status. Root Holding Bit. Attempts to become the root during next bus reset if set to "1". Initiate Bus Reset. Generates bus reset when possible after being set to "1". Cleared after bus reset. Gap Count. Used to optimize gap time according to bus scale. Indicates this node's highest speed; 200Mbps when "01", 100Mbps when "00". Indicates the number of ports on this node. Indicates port n TPA status. 11 = Z, 01 = 1, 10 = 0, 00 = invalid Indicates port n TPB status. 11 = Z, 01 = 1, 10 = 0, 00 = invalid When the value is "1", indicates that port n is the Child. "0" indicates Parent. When the value is "1", indicates that the active cable is connected to port n. When the value is "1", indicates that port n supports 200Mbps. This is set to "1" when Tree-ID is not completed in time, which means that the bus may be forming a loop. Indicates a drop in cable power line voltage. Same as CPS. Indicates that this node generates the last bus reset. More than one node may set this value. Indicates an illegal LReq is detected. Indicates the chip revision number. Indicates XSLOW pin is set to LOW. When set to "1", the node acts as a 100Mbps PHY. Default is "0". Initiate the arbitrated bus reset. Cleared after bus reset. 50MHz Ping Timer count. A count starts when a configuration packet is transmitted and stops when the first packet is received. The value may not be cleared until the next configuration packet is sent.
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CXD1944R
External Components and Pin Connection
220pF 20pF 2.4k
20pF 6.6k VDD DVSS 64 DVSS 63 /ISO XISO 62 AVSS 61 R1 60 R0 59 VDD DVDD 58
20pF 100k
VDD XO 57 XI 56 AVDD 55 FLT 54 AVSS 53 AVSS 52
VDD AVDD 51 AVSS 50 AVSS 49 TPB3 48 TPB2 47 TPB1 46 TPB1+ 45 TPA1- 44 TPB1+ 43 TPB1- 42 AVSS 41 TPA2+ 40 TPA2- 39 TPB2+ 38 TPB2- 37 TPA3+ 36 Tp Cables Tp Cables Tp Bias TPA3- 35 TPB3+ 34 32 AVSS 31 CNA 28 PC0 30 PC2 29 PC! TPB3- 33
1 XRESET 0.1F LINK VDD 10k 2 LPS 3 LREQ 4 VDD-IO LDSEL VDD Power Down 5 LDSEL 6 DVDD 7 PWD 8 DVSS 9 SYSCLK 10 DVSS LINK Controller Interface 11 CTL0 12 CTL1 13 D0 27 CMC/LKON 14 D1 19 XSLOW 15 D2 17 CAP 18 TIO 16 D3 21 TEST1 22 TEST0
20 DVDD
24 AVDD
25 AVDD
0.1F
200k
26 AVSS
23 CPS
VDO /SLOW
VDD Cable Power
Power Class Programming 10k CNA Out
Link On Configuration
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CXD1944R
Twisted Pair Cable Connection
CPS 200k TPAn+ TPAn- 55 Cable Port (n) TPBn+ TPBn- TPBSn 0.33F 250pF 5k Cable pair B 55 Cable pair A Power pair
55
55
Description of Operation The CXD1994R is used with LINK controllers such as the CXD1940R to configure a high speed serial bus. It has three ports which support speeds of 100M/200Mbps. There are four basic operations which may occur in the interface: request, status, transmit, and receive. All bit request are initiated by the PHY. The LINK uses the
request operation to read or write an internal PHY register or to ask the PHY to initiate a transmit action. The PHY initiates a receive action whenever a packet is received from the serial bus. The serial bus is always 2 bits wide, independent of speed. The encoding of these pins is as follows:
CTL [0 : 1] When PHY is Driving CTL [0: 1] 00 01 10 11 Name Idle Status Receive Transmit No activity. The PHY is sending status information to the LINK. An incoming packet is being transferred from the PHY to the LINK. The LINK is granted the bus to send a packet. Meaning
CTL [0 : 1] When the LINK is Driving (upon a grant from PHY) CTL [0: 1] 00 01 10 11 Name Idle Hold Transmit Reserved Meaning Transmission complete, release bus. The LINK is holding the bus while preparing data or indicating it wishes to reacquire the bus without arbitration to send another packet. The LINK is sending a packet to the PHY. Unused.
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CXD1944R
LINK Request To request the bus or access a PHY register, the LINK sends a short stream to the PHY on the LREQ pin. The information sent includes the type of request to which the packet is to be sent, or a read or write command. The
transfer can be either 7 bits, 9 bits or 17 bits, depending on whether it is a bus request, a read access, or a write access, repectively. A stop bit of 0 is required after each request transfer before another transfer may begin.
Bus Request Format Bit(s) 0 1 to 3 4 to 5 Name Start Bit Request Type Request Speed Description Indicates start of transfer. Always 1. Indicates which type of bus request is being performed. See the table below for the encoding of this field. The speed at which the PHY will be sending the packet for this request. This field has the same encoding as the speed code from the first symbol of the receive packet. See the following table for the encoding of this field. Indicates end of transfer. Always 0.
6
Stop Bit
If the transfer is a read request, it is 9 bits long and has the following format: Read Request Format Bit(s) 0 1 to 3 4 to 7 8 Name Start Bit Request Type Address Stop Bit Description Indicates start of transfer. Always 1. Indicates that this is a register read. See the following table for the encoding of this field. The internal PHY register address to be read. Indicates end of transfer. Always 0.
If the transfer is a write request, it is 17 bits long and has the following format: Write Request Format Bit(s) 0 1 to 3 4 to 7 8 to 15 16 Name Start Bit Request Type Address Data Stop Bit Description Indicates start of transfer. Always 1. Indicates that this is a register read. See the following table for the encoding of this field. The internal PHY register address to be written. The data to be written to the specified address. Indicates end of transfer. Always 0.
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CXD1944R
The request type field is encoded as follows: Request Type Field LREQ [1 : 3] 000 001 010 011 100 101 110 to 111 Name ImmReq IsoReq PriReq FairReq RdReq WrReg Reserved Meaning Take control of the bus immediately upon detecting idle; do not arbitrate. Used for acknowledge transfers. Arbitrate for the bus; no gaps. Used for isochronous transfers. Arbitrate after a subaction gap; ignore fair protocol. Used for cycle start packet. Arbitrate after a subaction gap, following fair prototcol. Used for fair transfers. Return specified register contents through status transfer. Write to specified register. Ignored.
The request speed field is encoded as follows: Request Speed Field LREQ [4 : 5] 00 01 10 11 Data Rate 100Mbps 200Mbps 400Mbps >400Mbps
NOTE: The CXD1944R does not support 400Mbps and over.
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CXD1944R
LREQ Timing
LR0 LR1 LR2 LR3 LR (n - 2) LR (n - 1)
FairReq and PrioReq: To request the bus for fair or priority access, the LINK sends the request at least one clock after the interface becomes idle. The LINK interprets the receive state on the CTL pins as a lost request. If the LINK sees the receive state anytime during or after it sends the request transfer, it assumes the request is lost and reissues the request on the next idle. The PHY will ignore a fair or priority request if it asserts the receive state anytime during the request transfer. Note that the minimum length of a packet is two clock cycles in the case of 400Mbps acknowledge packet. The minimum request packet is 8 clock cycles. It is important that the LINK and PHY agree to interpret a lost request the same way. The cycle master node uses a priority request (PriReq) to send the cycle start message. To request the bus to send isochronous data, the LINK can issue the request at any time after receiving the cycle start. The PHY will clear an isochronous request only when the bus has been won. ImmReq: To send an acknowledge, the LINK must issue an ImmReq request during the reception of the packet addressed to it. This is required because the delay from end of packet to acknowledge request adds directly to the minimum delay every PHY must wait after every packet to allow an acknowledge to occur. After the packet ends, the PHY immediately takes control of the bus and grants the bus to the LINK. If the header CRC of the packet turns out to be bad, the LINK releases the bus immediately. The LINK cannot use this grant to send another type of packet. To ensure this, the LINK must wait 160ns after the end of the received packet to allow the PHY to grant it the bus for the acknowledge, then release the bus and proceed with another request. Though highly unlikely, it is conceivable that two different nodes can perceive (one correctly, one mistakenly) that an incoming packet is intended for them and both issue an acknowledge request before checking the CRC. Both nodes' PHYs would grab control of the bus immediately after the packet is complete. This condition will
cause a temporary, localized collision of the data-on line states somewhere between two PHYs intending to acknowledge. All other PHYs on the bus would see the data-on state. This collision would appear as a "zz" line state, and would not be interpreted as a bus reset. The mistaken node would drops its request as soon as it has checked the CRC and spurious "zz" line states would go away. The only side effect of such a collision would be the loss of the intended acknowledge packet, which would be handled by the higher-layer protocol. IsoReq: To send an isochronous packet, the LINK is recommended to issue an IsoReq request during the reception or transmission (if root) of a cycle start packet or another isochronous packet. This is required to keep an isochronous gap short. Any IsoReq will be cleared when a packet is transmitted or a certain time (80ns) is passed in idle after the bus seized. (This timeout is not a part of the IEEE1394-1995 standard.) When the LINK issues an IsoReq before CRC check of a cycle start packet and the CRC is found wrong after the IsoReq, the LINK may release the bus without sending a packet when the bus is granted. Read/Write Request: For write requests, the PHY takes the value in the data field of the transfer and loads it into the addressed register as soon as the transfer is complete. For read requests, the PHY returns the contents of the addressed register at the next opportunity through a status transfer. The LINK is allowed to perform a read or write operation at any time. If the status transfer is interrupted by an incoming packet, the PHY continues to attempt the transfer of the requested register until it is successful. Once the LINK issues a request for access to the bus (immediate, iso, fair, or priority) it cannot issue another request until the PHY indicates "lost" (incoming packet) or "won" (transmit). The PHY ignores new requests while a previous request is pending.
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CXD1944R
Status Transfer When the PHY has status information to transfer to the LINK, it will initiate a status transfer. The PHY will wait until the interface is idle to perform the transfer. The PHY initiates the transfer by asserting status (01b) on the CTL pins, along with the first two bits of status information on D [0 : 1]. The PHY maintains CTL = status for the dura-
tion of the status transfer. The PHY may prematurely end a status transfer by asserting something other than status on the CTL pins. This should be done in the event that a packet arrives before the status transfer completes. There must be at least one cycle in between consecutive status transfers.
Status Transfer Timing
PHY CTL [0:1]
00
01
01
01
00
00
PHY D [0:1]
00
s[0:1]
s[2:3]
s[14:15]
00
00
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CXD1944R
Transmit: When the LINK requests access to the serial bus through the LREQ pin, the PHY arbitrates for access to the serial bus. If the PHY wins the arbitration, it grants the bus to the LINK by asserting transmit on the CTL pin for one SCLK cycle, followed by idle for one cycle. After sampling the transmit state from the PHY, the LINK takes over control of the interface by asserting either hold or transmit on the CTL pins. The LINK asserts hold to keep ownership of the bus while preparing data. The PHY asserts the data-on state on the serial bus during this time. When it is ready to begin transmitting a packet, the LINK asserts transmit on the CTL pins along with the first bits of the packet. After sending the last bits of the packet, the link asserts either idle or hold on the on the CTL pins for one cycle, and then idle for one additional cycle before tristating those pins. The hold state here indicates to the PHY that the LINK needs to send another packet without releasing the bus. The PHY responds to this hold state by waiting the required minimum time and then asserting transmit as before. This function would be used after sending an acknowledge if the LINK intends to send a unified response, or to send consecutive isochronous packets Transmit Timing
Single Packet PHY CTL [0:1] PHY D [0:1] LINK CTL [0:1] LINK D [0:1] 00 00 zz zz zz zz
during a single cycle. The only requirement when sending multiple packets during a single bus ownership is that all must be transmitted at the same speed, since the speed of the packet transmission is set before the first packet. As noted above, when the LINK has finished sending the last packet for the current bus ownership, it releases the bus by asserting idle on the CTL pins for two SCLK cycles. The PHY begins asserting idle on the CTL pins one clock after sampling idle from the link. Note that whenever the D and CTL lines change "ownership" between the PHY and the LINK, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals, rather than having to respond to a CTL state on the next cycle. Note that it is not required that the LINK enter the hold state before sending the first packet if implementation permits the LINK to be ready to transmit as soon as bus ownership is granted. The timing for a single packet transmit operation is shown below. In the diagram, D0 through Dn are the data symbols of the packet; zz represents high impedance state.
11
zz
zz
zz
zz
00
00
00
00
zz
zz
zz
zz
zz
zz
zz
zz
00
zz
zz
zz
01
01
10
10
10
10
00
00
zz
zz
zz
zz
00
00
D0
D1
D2
Dn
00
00
zz
Continued Packet PHY CTL [0:1] PHY D [0:1] LINK CTL [0:1] LINK D [0:1] zz zz zz zz 00 00 11 00 zz zz zz zz
zz
zz
zz
zz
00
00
00
00
zz
zz
zz
zz
10
10
01
00
zz
zz
zz
zz
01
01
10
10
Dn-1
Dn
00
00
zz
zz
zz
zz
00
00
D0
D1
NOTES: zz = Hi-Z D0 to Dn = Packet data This figure is for 100Mbps. For 200Mbps, D [0:3] is used.
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CXD1944R
Receive: Whenever the PHY sees the "data-on" state on the serial bus, it initiates a receive operation by asserting receive on the CTL pins and "1" on each of the D pins. The PHY indicates the start of a packet by placing the speed code (encoding shown below) on the D pins, followed by the contents of the packet, holding the CTL pins in receive until the last symbol of the packet has been transferred. The PHY indicates the end of the packet by asserting idle on the CTL pins. Note that the speed code
is a PHY-LINK protocol and is not included in the calculation of the CRC or other data protection mechanisms. It is possible that a PHY can see date-on appear and then disappear on the serial bus without seeing a packet. This is the case when a packet of a higher speed than the PHY can receive is being transmitted. In this case, the PHY will end the packet by asserting idle when the dataon state goes away. If the PHY is capable of a higher data rate than the LINK, the LINK detects the speed code as such and ignores the packet until it sees the idle state again.
Receive Timing
PHY CTL [0:1] 00 10 10 10 10 10 10 00 00
PHY D [0:3] (hex)
0
F
F
SPD
D0
D1
Dn
0
0
NOTES: SPD = speed code D0 to Dn = data symbols of the packet; for 100Mbps, packet data is output to D [0 : 1] only.
The speed code for the receive operation is defined as follows: Receive Speed Code D[0 : 3] 00xx 0100 Data Rate 100Mbps 200Mbps
NOTE: The "xx" means transmitted as 00, ignored on receive.
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CXD1944R
Power Class Programming Power use or power supply from the cable requires certain settings. PC [2 : 0] is used for this setting. The power classes are defined as follows:
PC [2 : 0] 000 001 010 011 100 101 110 111
Definition The node does not consume cable power. Also, power does not repeat. The node operates on its own power, and a minimum of 15W is supplied to the cable. The node operates on its own power, and a minimum of 30W is supplied to the cable. The node operates on its own power and a minimum of 45W is supplied to the cable. The node may use cable power. Maximum required power is 1W. The node may use cable power. Maximum required power is 1W. A further 2W are required to operate LINK and upper layer. The node may use cable power. Maximum required power is 1W. A further 5W are required to operate LINK and upper layer. The node may use cable power. Maximum required power is 1W. A further 9W are required to operate LINK and upper layer.
Additional Features Short Bus Reset: The short bus reset or arbitrated bus reset were proposed in the 1394 Trade Association by Apple Computer. The standardization, however, has not been done yet. The CXD1944R supports a short bus reset mode whose reset pulse width is 1.4s instead of the normal bus reset pulse width of 166s. This mode can be selected by connecting the TIO pin to VDD. When the node needs to send a reset pulse, it will first arbitrate the bus according to the fair protocol as a FairReq. If it gets the bus grant, it will send a short bus reset pulse instead of a packet. This is called "arbitrated bus reset", which ensures all nodes can detect the short bus reset pulse. Since it follows Fair protocol, it won't disturb the isochronous cycle. This arbitrated bus reset can only work after the bus is initialized. Before the bus initialization, the node will send a short bus reset pulse immediately. In both cases, if a short bus reset fails, the node will send a normal long bus reset, so that the short bus reset mode can be used with an older PHY which does not support a short bus reset mode. If the IBR bit of the internal PHY register is set to 1, the device will send a long reset pulse. To request a short arbitrated bus reset, write 1 to the ArbRsrReq bit in the reset mode.
Slow Mode: The CXD1944R supports 200Mbps. In some cable environments, however, 200Mbps may be difficult to operate; thus we have added the Slow Mode operation. By connecting XSLOW pin to ground, or writing a "1" to the Slow Bit of the internal PHY register, the device will act as a 100Mbps PHY. D[2:3] is still active in the slow mode. Ping and Ping Timer: Ping is used to measure a node-node packet delay. If the node received an R=0 and T=0 configuration packet, it will send a Self-ID packet immediately as an acknowledge. Since a LINK is not involved in this Self-ID transmission, and it is very quick, a sender can know the exact packet delay between the node and the remote node. LINK can read a Ping timer count after a Self-ID acknowledge. The Ping timer will be cleared and starts a count only when a configuration packet is sent from the node. The counter runs at 50MHz clock cycle. This feature is thought useful to optimize a gap count of the bus.
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CXD1944R
Package Outline
Unit: mm 64 pin LQFP (Plastic)
12.0 0.2
*
48 49
10.0 0.1 33 32
0.127 +0.05 -0.02
0.1
64
17 (0.22) 1
+0.08
16
+0.2
0.5 0.08
0.18 -0.03
1.5 -0.1
0.1 0.1
0-10 NOTE: Dimension "*" does not include mold protrusion.
Package Structure SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 *QFP064-P-1010-A -- PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY 0.3g
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0.5 0.2
0.5 0.2 (11.0)

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